Recent advances in MOS technology, and in particular the development of practical solutions to the problems associated with the construction of thin tunnel dielectrics, have led to the successful design and manufacture of non-volatile memory cells having both electrical programming and electrical erasing capabilities. U.S. Pat. No. 4,115,914 issued to Harari on Sept. 26, 1978; U.S. Pat. No. 4,203,158 issued to Frohman-Bentchkowsky et al on May 13, 1980 and co-pending application Ser. No. 343,847, filed Jan. 29, 1982 and assigned to the assignee of the present invention, for example, all disclose semiconductor storage devices adapted for use in an MOS memory cell, wherein the storage devices employ thin tunnel dielectrics to facilitate electrical programming and electrical erasing of the cell. The structures of both the Harari and Frohman-Bentchkowsky et al storage devices include a floating gate disposed above the surface of a substrate and insulated therefrom by an oxide layer. The major portion of the oxide layer is relatively thick, i.e., 500 A to 1,000 A, but a remaining portion of the oxide comprises a thin tunnel dielectric on the order of 20A to 200A which separates the floating gate from an active substrate region contiguous with the storage device source, drain or channel region. When a suitable unipolar potential is applied to a control gate vertically-aligned with the floating gate, charge carriers can be tunneled from the active substrate region through the thin dielectric to the floating gate. Similarly, application of another unipolar potential to the active substrate region causes charge carriers present on the floating gate to tunnel back out of the floating gate through the thin tunnel dielectric and into the active substrate region.
In addition to disclosing the structure and operation of electrically-programmable and electrically-erasable storage devices, the aforementioned Harari and Frohman-Bentchkowsky et al patents teach a series of process flow steps whereby the storage devices are formed. For the most part, these process flow steps are conventional in nature, merely involving a collection of known MOS fabrication techniques arranged in a predetermined sequence calculated to yield the desired storage device configuration. Where, however, storage device components are fundamentally rearranged for the purpose of improving memory cell programming and erasing performance as disclosed in the aforementioned co-pending application Ser. No. 343,847, the prior art teachings associated with prior art configurations provide little guidance in establishing a sequence of process flow steps appropriate to the new and improved storage device configurations.